1. Field of Invention
The present invention relates in general to a duty cycle compensation circuit of a delay locked loop (DLL) in a Rambus DRAM. More specifically, the inventions claimed herein feature, in part, a duty cycle compensation circuit of a delay locked loop (DLL) capable of reducing power consumption by reducing the time for escaping from a nap mode and extending the time for maintaining the nap mode. This is accomplished by safely storing information even in case of a long nap mode digitalizing an analog duty information of a clock input signal in the nap mode, and immediately using the information re-analogized from digital information of the clock signal that is stored when escaping from the nap mode.
2. Description of Related Art
A DLL circuit which is part of a system receives an externally generated clock signal input, synchronizes it with a clock signal generated within the system, and outputs it. The DLL may be applied to a cash memory unit (xe2x80x98SRAMxe2x80x99 is generally used.) increasing a data process speed between the CPU of a computer and a DRAM as well as various kinds of logical devices or to a synchronous DRAM and a Rambus DRAM. The duty cycle compensation circuit used in the DLL is a circuit that compensates a duty of an inner clock used in a direct Rambus DRAM.
In general, the Rambus DRAM has various modes of operation such as, for example, active mode, standby mode, and nap mode to operate a system with low electric power drain. Rambus DRAM in operating in its active mode is ready to transmit data at any time and consumes more electric power than it does in its other modes of operation.
In a general DRAM memory system, all memory banks of respective devices consume electric power for reading/writing through the over-all access command, while in the Rambus DRAM memory system, reading/writing are performed through only one device after the other devices are converted into a state of low electric power.
Rambus DRAM is automatically changes to standby mode operation at the last step of transmission. When a request packet is decoded so as to specify the address of a particular device, the other (non-addressed) Rambus DRAMs return to the standby mode, leaving only the addressed device in a more active mode. The addressed device returns to the standby mode when the reading or writing operation ends.
In other words, Rambus DRAMs tend to return to the standby mode. Due to this default mode property, the other Rambus DRAMS remain on the standby mode while only a selected Rambus DRAM changes to active mode operation, thereby minimizing consumption of electric power.
Causing one or more Rambus DRAMs to operate in a nap mode may reduce the consumption of electric power. Nap mode operation consumes less electric power than standby mode operation. A device can change from nap mode to active mode faster than it can change from powerdown mode to active mode. Whenever the system is not reading or writing, the Rambus DRAM changes its mode of operation to nap mode thereby largely reducing the consumption of electric power. When one or more Rambus DRAMS change to power down mode, the greater effect of reduction in electric power can be obtained.
When the Rambus DRAM is in the nap mode, all bias power is off and no inner clock is generated. However, all bias power is on when escaping from the nap mode thereby generating an inner clock.
FIG. 1 shows a known circuit arrangement having a power save mode function for a Rambus DRAM. The circuit arrangement includes a packet controller 200, a power mode controller 300, a DLL 400, and a memory core 100. The packet controller 200 receives a control packet signal ctrl13 PKT applied from the external channel of the memory and generates a control signal cntrl controlling whether the power mode is possible or not and an OP_code defining each operation mode.
The power mode controller 300 respectively generates a self refresh enable signal_self_refresh en and power mode signals (a nap mode signal Nap and a power down mode signal PDN) by combining the signals (OP_code and the cntrl) from the packet controller 200. At this time, the self-refresh enable signal self_refresh_en performs a self-refresh operation by operating the refresh counter (not shown) provided at the inside or outside of the memory core 100.
Meanwhile, the nap mode signal Nap and the power down mode signal PDN from the power mode controller 300 are transmitted to the DLL 400 thereby controlling the operation of the DLL 400 depending on each power mode.
The DLL 400 is controlled by the nap mode signal Nap and the power down mode signal PDN, receives the clock signal clk_in from the external channel, detects the phase difference between the clock signal clk_in and the clock signal used in a semiconductor memory, adjusts them so that no phase difference exists, and generates a locked signal showing the possibility to be changed to a normal operation mode by the power mode controller 300.
FIG. 2 is a block construction diagram of the DLL 400 shown in FIG. 1. DLL 400 comprises a control unit 410, a bias generation unit 420, a duty cycle compensation unit 430, a phase detection and mix unit 440, a clock amplification unit 450, and a clock buffer unit 460.
The phase detection and mix unit 440 receives the clock signal clk_in from the external channel, and outputs a signal obtained by detecting the phase difference between a clock signal clk_in from the external channel and the clock signal clk_out used in the semiconductor memory and mixing the clock signals clk_in and clk_out.
The clock amplification unit 450 amplifies the output signal from the phase detection and mix unit 440, and outputs the amplified signal to the clock buffer unit 460. The duty cycle compensation unit 430 compensates for the phase difference between the clock signal clk_in the clock signal clk_out by the PDM signal from the control unit 410, and stores duty information into a capacitor by the nap mode signal from the control unit 410. The bias generation unit 420 is operated by the nap mode signal from the control unit 410 and generates a bias signal. The control unit 410 controls the operation of each circuit by the nap mode signal Nap and the power down mode signal PDN from the power mode controller 300.
FIG. 3 is a circuit diagram of the duty cycle compensation unit 430 shown in FIG. 2. The duty cycle compensation unit 430 comprises a differential amplification stage 432 controlling output signals in the nap mode (napb signal is xe2x80x98lowxe2x80x99) and respectively outputting the differentially amplified signals of the input clock signals (clki and clkib) to output nodes (Nd6 and Nd7) in the other operation modes (napb signal is xe2x80x98highxe2x80x99), a signal transmission switching stage 434 respectively switching output signals from the differential amplification stage 432 to a first terminal as a signal dccb and a second terminal as a signal dcc, and a storage capacitor stage 436 storing the data signals dccb and dcc.
The differential amplification stage 432 is operated by a signal vbiasn from the bias generation unit 420, differentially amplifies clock signals clki and clkib when a power reset signal PwrRst is xe2x80x98lowxe2x80x99, a nap mode bar signal napb is xe2x80x98highxe2x80x99, and a capacitor on signal capon is xe2x80x98highxe2x80x99, and outputs the amplified signal to the output terminals.
The detailed operation of the differential amplification stage 432 will now be described. First, when the signal vbiasn is enabled to a xe2x80x98highxe2x80x99 level, NMOS transistors N3, N4, and N5 and PMOS transistors P1 to P3 functioning as a current source are turned on thereby operating the differential amplification stage 432.
Afterwards, when the nap mode bar signal napb is xe2x80x98highxe2x80x99 level (not in the nap mode but in the other operation modes), a NMOS transistor N6 is turned on and the potential level at the node Nd5 is dropped to a ground potential level Vss through NMOS transistors N5 and N6 which are turned on. As the potential level at the node N5 goes downward the ground potential level Vss, a PMOS type diode P4 and PMOS transistors P5 to P7 having current mirror type structures are turned on.
Potential levels at nodes Nd1 and Nd2 are differentially amplified by the operations of NMOS transistors N1 and N2 that are on/off by the input signals clki and clkib. The amplified signals at the nodes Nd1 and Nd2 are transmitted to output nodes Nd6 and Nd7 of the differential amplification stage 432 through PMOS transistors P6 and P7, which are turned on. At this time, at the node Nd6 or Nd7 being xe2x80x98highxe2x80x99 level, its level is converted into xe2x80x98lowxe2x80x99 level because a current path is formed to the Vss through NMOS transistors N9, N10, N15, and N16 that are turned on by the nap mode bar signal napb. At the node Nd6 or Nd7 being xe2x80x98lowxe2x80x99 level, its level is converted into xe2x80x98highxe2x80x99 level by the voltage supplied through PMOS transistors P2 and P6, and PMOS transistors P3 and P7 having current mirror type structures because a current path is not formed to the Vss.
Accordingly, the differentially amplified signal is output to the nodes Nd6 and Nd7 according to the clock signal clki and clkib in an interval when the bias voltage signal Vbiasn is xe2x80x98highxe2x80x99, the nap mode bar signal napb is xe2x80x98highxe2x80x99, and the power reset signal PwrRst is xe2x80x98lowxe2x80x99.
In the meantime, since the bias voltage signal Vbiasn is xe2x80x98highxe2x80x99, the nap mode bar signal napb is xe2x80x98lowxe2x80x99, and the power reset signal PwrRst is xe2x80x98highxe2x80x99 in the Nap mode operation, the NMOS transistor N6 is turned on and the PMOS transistor P8 is turned on thereby making the potential at the node Nd5 into xe2x80x98highxe2x80x99. Consequently, the diode P4 and the current mirror type PMOS transistors P5 to P7 are off. NMOS transistors N9, N10, N15, and N16 are turned off thereby controlling the operation of the differential amplification stage 432. At this time, the output nodes Nd6 and Nd7 are equalized by a PMOS transistor P13.
The signal transmission switching stage 434 comprises transmission gates P9 and N19 transmitting the signal from the node Nd6 to the output terminal outputting the signal dccb according to the control signal capon from an input terminal and the control signal capon from other input terminal, a capacitor N21 connected between the output terminal outputting the dccb and the input terminal receiving the signal caponb, and capacitor P10 connected between the output terminal outputting the signal dccb and the other input terminal receiving the signal capon. Herein, the transmission gates P9 and N19 are comprised of PMOS and NOMS respectively, the capacitor N21 is comprised of NMOS, and the capacitor P10 is comprised of PMOS. And also the signal transmission switching stage 434 comprises transmission gates P12 and N20 transmitting the signal at the node Nd7 to the output terminal outputting the signal dcc according to the control signal capon from the input terminal and the control signal caponb from the input terminal, a capacitor N22 connected between the output terminal outputting the signal dcc and the input terminal receiving the signal capon, and capacitor P11 connected between the output terminal outputting the signal dcc and the input terminal receiving the signal capon. Herein the transmission gates P12 and N20 are comprised of PMOS and NOMS respectively, the capacitor N22 is comprised of NMOS, and the capacitor P11 is comprised of PMOS.
The signal transmission switching stage 434 switches the signal from the differential amplification stage 432 to a capacitor stage 436 connected to the output stage according to the control signals capon and caponb. Herein, the control signal capon disconnects the path between the output terminals Nd6 and Nd7 of the differential amplification stage 432 and the output terminals outputting the signals dcc and dccb since the control signal capon is xe2x80x98lowxe2x80x99 in the nap mode (the signal napb is xe2x80x98lowxe2x80x99), while the control signal capon transmits duty information of the input signals clki and clkib from the differential amplification stage 432 to the output terminals since the control signal is xe2x80x98highxe2x80x99 in the other operation modes(the napb signal is xe2x80x98highxe2x80x99).
The storage capacitor stage 436 comprises NMOS type capacitors N23 and N24 that are respectively connected between the output terminals and the ground Vss. The NMOS type capacitors N23 and N24 store duty information to be output to the output terminals in the nap mode for a predetermined time.
FIG. 4 shows a circuit for generating the control signal napb shown in FIG. 3. The circuit comprises three inverters INV1, INV2 and INV3 connected in series. The inverter INV1 receives the signal Nap, and the inverter INV3 outputs the signal napb. Herein the nap mode bar signal napb has low level in the nap mode.
FIG. 5 shows a circuit for respectively generating the control signals capon and caponb as shown in FIG. 3 using a the hold signal DLLhold from DLL. The circuit for generating the control signals capon and caponb comprises four inverters INV4 to INV7 connected in series between a terminal receiving the signal xe2x80x98DLLholdxe2x80x99 and a terminal outputting the control signal caponb, and an inverter INV8 connected between the terminal outputting the control signal caponb and the terminal outputting the control signal capon.
The control signal capon is xe2x80x98lowxe2x80x99 and the control signal caponb is xe2x80x98highxe2x80x99 in the Nap mode (the napb is xe2x80x98lowxe2x80x99).
The duty cycle compensation unit 430 in the DLL 400 as shown in FIG. 3 stores duty information in the capacitor of the output stage when the Rambus DRAM is in the Nap mode, and uses the information in the normal operation. However the conventional duty cycle compensation unit having such a construction may lose the stored duty information due to leakage current generated in the capacitor in case the operation time of the nap mode is long. Due to this, it is further required the time necessary for compensating the information lost when escaping from the nap mode. Consequently, the consumption of the power is increased and the escape time is very long.
The inventions claimed herein feature, at least in one respect a duty cycle compensation circuit of a delay locked loop (DLL) capable of reducing power consumption by reducing the time necessary for escaping from a nap mode and extending the time for maintaining the nap mode. The DLL for Rambus DRAM according to the present invention comprises: a duty cycle compensation arrangement that compensates a duty cycle of an input signal in modes of operation other than nap mode, and stores the duty information of the compensated input signal into a capacitor in the nap mode. An analog-to-digital converter arrangement converts the compensated input signal from the duty cycle compensation arrangement into a digital signal according to a first control signal, and maintains the converted digital signal regardless of the input signal when the first control signal is disabled. A digital-to-analog converter converts the digital signal from the analog-to-digital converter arrangement into an analog signal according to a second control signal, and being turned off when the second control signal is disable; and a control means for respectively generating the first and second control signals depending on whether or not the nap mode operates.
In the duty cycle compensation circuit of the DLL for the Rambus DRAM according to the present invention, the control means disables the first and second control signals in the other operation modes than the nap mode, enables the first control signal in the nap mode, and enables the second control signal in escaping from the Nap mode.
The control means disables the first control signal when the conversion from the analog signal to digital signal is completed. The control means disables the second control signal when the conversion from the digital signal to analog signal is completed.